Silicon dioxide in its crystalline form (quartz) as well as its amorphous form (glass) is finding increasing applications in microsystems, as active resonator structure as well as passive support and packaging components. Recently borosilicate glass and quartz substrates have been etched with high aspect ratios and high surface smoothness using SF6 and Ar/Xe gases [1-3]. The main focus of these etch process development has been the achievement of high etch rates and high aspect ratio etching of silica. In this context the processes developed thus far rely upon ion bombardment to accelerate the etching process while fluorine based gases are used to provide the reactive component for etching. The use of heavier Xe helps reduce the re-deposition and more effectively removes any non-volatile residues resulting in smoother surfaces with an average surface roughness of ˜2 nm.
In spite of more than an order of magnitude increase in the etch rate of silicon dioxide compared to comparable processes used in CMOS industry, the currently obtained etch rates are not attractive enough for MEMS through wafer and high aspect ratio etching of glass substrates. Considering that typical glass substrates are 100-500 μm, these etches can take between 200 (˜3 hours) and 1000 minutes (˜16 hours) at a rate of ˜0.5 μm/min making such processes impractical for glass based device development and their commercialization. Etch processes that can potentially break through this etch rate limitation for glass can dramatically affect several MEMS devices—including inertial and microfluidic devices. Thus, the question to ask is what is limiting the etch rate of silica at just under the 1 μm/min.
To date, efforts in silicon dioxide (glass) etching, have been primarily directed towards realizing features for microelectronics applications such as interconnect vias [5], waveguides [6], phase shift masks [7], etc. Hence, process optimization has traditionally aimed at increasing the selectivity of silicon dioxide over silicon substrate [8], reducing gate oxide damage [9], decreasing sidewall roughness [10], and increasing sidewall angle of the etched features [11]. With the advent of microelectromechanical systems (MEMS) and microsystems in the last decade, focus has shifted to high aspect ratio etching of silicon dioxide for applications in microfluidics [12], microsensors [13], and lab-on-a-chip applications. Many of these applications require greater than 100 μm of silicon dioxide (glass) etching while maintaining the surface finish, with RMS surface roughness of less than 5 nm [14, 15]. Hence, these applications impose additional new requirements on borosilicate glass etching processes such as high etch rate, high selectivity to masking material, high anisotropy, low surface roughness for mirror polish, uniformity of etch across the wafer and within a pattern [16], etc.
Traditional RIE processes are limited by the fact that the substrate power and RF plasma power are coupled to each other often resulting in etch non-uniformity across the wafer, low density of plasmas, and limited control over the processing conditions. However, in an inductively coupled plasma (ICP) RIE system, the substrate power and the coil (source) power are independent of each other thus providing excellent control over plasma density (controlled by ICP power) and energy of etchant ions (controlled by substrate power) [17]. As a result, plasma can be generated even at relatively low pressures in the range of 10−4 Torr to 10−3 Torr. However, at such low pressures, the plasma in traditional RIE systems is not stable.
Nonetheless, low processing pressure is advantageous for rapid removal of etching products from the surface and also for the removal of stray particles generated from the masking material, substrate holder and walls of the reaction chamber. The presence of stray particles results in micro-masking wherein the micro-particles or reaction products on the substrate shield the surface from the etchant species resulting in surface roughness, micro-trenching and formation of plateau-like structures. Additionally, the increased mean free path at low pressures improves the anisotropy of the etch by minimizing the randomizing collisions between the radicals, ions and other plasma species. Borosilicate glass substrates are known to have a typical composition of SiO2 (79.6%), B2O3 (12.5%), Na2O (3.72%), Al2O3 (2.4%), and K2O (0.02%).
In the case of deep reactive ion etching of silicon dioxide (quartz or borosilicate glass) a high Ar to SF6 ratio is required to maintain low RMS surface roughness. FIG. 1 shows the dependence of the etch rate and RMS surface roughness as a function of substrate RF power, chamber pressure, Ar, and SF6 flow rate. In all cases the pressure in the chamber was maintained at 0.26 Pa throughout the flow ranges. The ICP source power was 2000 W and a substrate bias power of 475 W (Bias Voltage of 80 V) was used in generating these results. From the graphs it can be seen that the best surface roughness of ˜2 nm is obtained at high Ar flow rates, low chamber pressure, and high substrate power—corresponding to conditions dominated by physical sputtering of the material. The etch rate can be increased by increasing the SF6 flow rate from 5 sccm to 50 sccm from 0.54 μm/min to 0.74 μm/min however the surface roughness was found to degrade under these conditions to >100 nm. Pulse electroplated nickel is typically used as the etch mask layer and a selectivity of ˜25:1 can be obtained for SiO2 etching under these conditions. FIG. 1(e) shows an SEM of a high aspect ratio feature etched in quartz using these conditions. Similar results were obtained by Li et al. while etching SiO2 using Xe instead of Ar. The higher sputter yield of Xe gave a lower RMS surface roughness value as compared to Ar for the same mole fraction of the inert gas in SF6. Although silicon grease or a small drop of a fluoropolymer based oil, such as FOMBLIN manufactured by Solvay S.A. of Belgium, Brussels, can be used for mounting the quartz/glass substrates onto a 4″ silicon carrier wafer, these materials cannot withstand the long process times and can leave the backside of the sample with hard to remove, stubborn residues. Furthermore, these mounting materials do not provide a reliable and uniform thermal contact, between the carrier wafer and the sample, throughout the entire etch process. In order to avoid these problems, indium solder can be used for mounting the sample directly onto a silicon wafer. However, the mounting side of the SiO2 sample needs to be coated with 20/80 nm of Cr/Au to provide a surface to which the solder can adhere. Of course if the sample is large enough it can be directly mechanically clamped or an electrostatic chuck can be used for the mounting of the sample. In all cases the backside of the chuck/substrate is cooled using helium gas maintained at the desired temperature.